1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to a semiconductor memory device having a defective cell write mode.
2. Description of the Background Art
As the degree of integration of semiconductor memory devices, particularly of dynamic RAMs (DRAMs) increases, power consumption in a standby state is ever increasing. Particularly in a DRAM, stored information is retained by re-reading/re-writing of stored information even in the standby state. Therefore, there is a limit in reducing the power consumption in the standby state in principle.
However, it is a critical issue to reduce as much as possible, the power consumption in the standby state in a system that uses a large number of DRAMs.
Increase in the degree of integration inevitably leads to increased possibility of defects in memory cells. In order to compensate for generation of error due to such defective memory cell, an approach by a so-called redundancy circuit is made where a column of memory cell including a defective memory cell is replaced by a spare column of memory cells, for example.
Such replacement allows the basic operation of reading/writing of data of a memory cell without any problem. However, even when the defect is repaired by the redundancy circuit, there still remains a leakage path at the defective portion. This means that the power consumption in the standby state of the DRAM is further increased.
The above circumstance will be described in detail with reference to FIG. 12.
The operation of each component will be described briefly.
In a Y address comparator circuit 6038 in a redundancy column decoder 6023, an address detected as including a defective bit at a time of previous testing is stored, in a nonvolatile memory such as a fuse circuit.
When an external address signal A0-Ai does not match the above identified address including the defective bit, a column selection line drive circuit 6034, for example, is activated, whereby a column selection line (hereinafter referred to as "CS line") 6024 is pulled up to an "H" level (logical high).
By an I/O gate 6018 of a bit line pair group unit 6102, for example, a pair of bit lines BL3, /BL3 is connected to a data input/output line 6020.
Potential difference between the pair of bit lines BL3 and /BL3 is amplified by a sense amplifier 6016 in accordance with the information stored in a memory cell connected thereto and selected by a signal of a word line, not shown.
By the above operation, the information of the memory cell is externally read out.
If there is a short-circuit portion 6200 between a bit line BL1 and the ground level GND, data cannot be read/written from and to the memory cell connected to that bit line.
In this case, the defective bit line is replaced by a spare bit line. Generally, this replacement is on a bit line by bit line basis or on unit by unit basis of the bit line pair group selected by a CS line.
More specifically, the address of CS line 6022 corresponding to the bit line pair group unit 6100 to which the defective bit line BL belongs is preprogrammed in a Y address comparator circuit 6038.
Externally applied address signal A0-Ai is compared with the programmed address of the defect by Y address comparator circuit 6038. When the two match each other, a signal (SE signal) activating a spare column decoder is input to a CS line drive circuit 6036, and a bit line pair group unit 6104 including spare bit lines SPARE BL1, SPARE /BL1 is selected.
At the same time, a signal (NED signal) inactivating the CS line associated with the defective bit line BL1 is input to a CS line drive circuit 6032.
Thus, defective bit is replaced and there is no problem in the basic operation of the memory cell.
However, the bit line pair is precharged to the level of a potential V.sub.BL generated by a bit line potential generating circuit (not shown) in the chip, for example, before sense amplifier 6016 starts amplifying operation in accordance with the information of the memory cell. Here, potential V.sub.BL is set to 1/2Vcc where Vcc represents the potential supplied from a power supply 6002.
Further, a first power supply line S2P to the sense amplifier connected through a switching transistor 6016 to power supply 6002 as well as a second power supply line S2N to the sense amplifier connected to the ground through switching transistor 6012 (hereinafter the power supply lines will be generally referred to as S2 line) are also precharged, similar to the bit line pair.
Therefore, a first leakage current path 6202 through which current leaks from the supply line of the potential of the bit line potential generating circuit through a bit line equalize circuit 6104 setting bit lines BL1 and /BL1 commonly to the potential V.sub.BL and through bit line BL1, and a second leak path 6204 through which current leaks from a S2 line equalize circuit 6008 setting S2 lines commonly to the potential V.sub.BL through the S2 line, sense amplifier 6016 and bit line BL1 are generated because of the existence of the short-circuit portion 6200.
As a result, a problem arises that the actual standby current at the memory cell portion increases.
Further, since the potential V.sub.BL attains lower than the designed value, operation margin with respect to V.sub.BL is significantly reduced. This will be described with reference to a timing chart of FIG. 13 showing the operation of the conventional DRAM.
First, at time t.sub.0, all the pairs of bit lines should be precharged to the level of potential V.sub.BL.
However, the potential of bit line pair BL1, /BL1 associated with the defective bit is lower than the potential V.sub.BL (1/2Vcc) because of the leakage current.
Line S2 of the sense amplifier is also lower than precharge voltage V.sub.BL, because of the leakage current. It is to be noted that reduction in potential of line S2 influences the operation of all the sense amplifiers commonly connected to line S2.
Following the transition of row address strobe signal /RAS from high ("H") to low ("L") at time t.sub.2, an internal signal BLEQ makes a transition from high to low at time t.sub.3, and the bit line pair is electrically isolated.
Similarly, S2 line equalize circuit 6008 is turned off, whereby the pair of lines S2 is electrically isolated.
Thereafter, at time t5, switching transistors 6010 and 6012 are turned on in response to signals /SOP and SON, respectively, and sense amplifier 6016 is activated.
As a result, potential of one of the paired bit lines BL1 and /BL1 and one of paired spare bit lines SPARE BL1 and SPARE /BL1 attains to the potential Vcc, and the potential of the other one of the paired line attains to the ground potential, in accordance with the information stored in the memory cell selected corresponding thereto. At time t.sub.8, at the transition of signals NED and SE from low to high, CS1 line 6022 is kept inactive while spare CS line 6026 is activated, and as a result, data is output to data input/output line (I/O line) 6020.
Thereafter, at time t.sub.12, signal /RAS makes a transition from low to high, and at time t.sub.13, the BLEQ signal makes a transition from low to high.
At the same time, the sense amplifier attains an inactive state by signals /SOP and SON. By the BLEQ signal, the bit line pair is again precharged to the potential V.sub.BL. However the potential of bit line pair BL1 and /BL1 lowers because of the leakage current, and the potential of S2 line also lowers.
As described above, the potential of S2 line immediately before activation of the sense amplifier is lower than V.sub.BL (=1/2Vcc) because of the leakage current. The resulting lower V.sub.BL would present more severe problem as the capacity of memories has been increased recently.
Increase in memory capacity and miniaturization of the device size require reduction in power supply voltage, from the stand point of reliability. Therefore, the problem of lower V.sub.BL margin caused by the reduction in voltage is further aggravated by the reduction of V.sub.BL due to leakage path.
As described above, the conventional semiconductor memory device suffers from a first problem that actual standby current of the memory cell portion is increased because of the leakage current at a defective portion and that operation margin with respect to the potential V.sub.BL is reduced.
Further, the conventional semiconductor memory device suffers from a second problem, which will be described in the following.
FIG. 14 is a partially omitted circuit block diagram showing a structure of a conventional DRAM and FIG. 15 is a partially omitted circuit block diagram showing, in detail, a structure of one column of memory cells shown in FIG. 14.
Referring to FIGS. 14 and 15, a memory cell array 6050 includes a plurality of memory cells MC arranged in a matrix, word lines WL provided corresponding to respective rows, and pairs of bit lines BL, /BL provided corresponding to respective columns.
Each memory cell MC is connected to the word line WL of the corresponding row. A plurality of memory cells MC of odd-numbered columns are connected to bit line BL or /BL alternately.
A plurality of memory cells of even-numbered columns are connected to bit line /BL or BL alternately.
Each memory cell MC includes an N channel MOS transistor 50 for accessing, and a capacitor 51 for storing information. N channel MOS transistor 50 of each memory cell MC has its gate connected to the word line WL of the corresponding row. N channel MOS transistor 50 is connected between the bit line BL or /BL of the corresponding column and one electrode (storage node SN) of capacitor 51 of the memory cell MC. Capacitor 51 of each memory cell MC receives, at the other electrode, a cell potential Vcp. The word line WL transmits an output from a row decoder 6020 and activates memory cells MC of the selected row. Bit line pair BL, /BL allows input/output of data signal to and from the selected memory cell MC.
A redundancy memory cell array 6052 has similar structure as memory cell array 6050 except that the number of columns is smaller than that of memory cell array 6050. Memory cell array 6050 and redundancy memory cell array 6052 have the same number of rows, and word lines WL are shared by memory cell array 6050 and redundancy memory cell array 6052.
A sense amplifier+input/output control circuit 6054 includes a column selection gate 6018, a sense amplifier 6016 and an equalizer 6014 which are provided corresponding to each column, and an intermediate potential generating circuit 6040 provided common to all the columns. Each column selection gate 6018 includes N channel MOS transistors 41 and 42 connected between bit lines BL and /BL and data signal input/output lines IO and /IO, respectively. N channel MOS transistors 41 and 42 have their gates connected to column decoder 6023a or 6023b through column selection line CSL. When column selection line CSL is pulled up to the high ("H") level, which is the selected level, by column decoder 6023a or 6023b, N channel MOS transistor 41 or 42 is rendered conductive and bit line pair BL, /BL is coupled to data signal input/output line pair IO, /IO.
Sense amplifier 6016 includes P channel MOS transistors 43 and 44 connected between a node N32 and bit lines BL and /BL, respectively, and N channel MOS transistors 45 and 46 connected between a node N32' and bit lines BL and /BL, respectively. MOS transistors 43 and 45 have their gates connected together to bit line /BL, while transistors 44 and 46 have their gates connected together to bit line BL. Nodes N32 and N32' receive sense amplifier activating signals SON and /SOP output from a clock generating circuit (not shown), respectively. Sense amplifier 6016 amplifies small potential difference between the pair of bit lines BL and /BL to power supply voltage Vcc, in response to sense amplifier activating signals SON and /SOP which have attained to "H" and "L" levels, respectively.
Equalizer 6014 includes an N channel MOS transistor 47 connected between bit lines BL and /BL, and N channel MOS transistors 48 and 49 connected between a node N33' and bit lines BL and /BL, respectively. N channel MOS transistors 47-49 have their gates connected to node N33. Node N33 receives a bit line equalize signal BLEQ, and node N33' receives a bit line potential VBL (=Vcc/2). Equalizer 6014 equalizes potentials of bit lines BL and /BL to bit line potential VBL in response to bit line equalize signal BLEQ which have attained to the active level of "H".
Intermediate potential generating circuit 6040 generates an intermediate potential Vcc/2 between power supply potential Vcc and ground potential GND, and outputs the generated intermediate potential Vcc/2 as bit line potential VBL.
Now, in such a DRAM, even when a defective memory cell is replaced by a redundancy memory cell MC, a normal memory cell near the defective memory cell MC may be affected by the defective memory cell and fails, dependent on the state of defective memory cell MC.
More specifically, referring to FIG. 16, a DRAM is formed on a surface of a p type silicon substrate 52. A gate electrode, that is, the word line WL is formed above the surface of p type silicon substrate 52 with a gate oxide film (not shown) interposed, and on the surface of silicon substrate 52 on both sides of word line WL, n.sup.+ source/drain regions 53 are formed, thus providing N channel MOS transistor 50 of memory cell MC. One of the source/drain regions 53 of N channel MOS transistor 50 is connected to bit line BL, and on the surface of the other one of the source/drain regions, a conductive layer 54, a dielectric layer 55 and a conductive layer 56 are stacked, thus providing capacitor 51 of memory cell MC. Conductive layer 54 serves as one electrode of capacitor 51, that is, a storage node SN, and conductive layer 56 serves as the other electrode of capacitor. Three memory cells MC1 to MC3 are formed in the figure.
Now, assume that there is a small conductive particle between the gate electrode of the central memory cell MC2, that is, word line WL2, and silicon substrate 52. Further, it is assumed that the particle is small enough to allow data writing though memory cell MC2 is defective, and that word line WL2 is driven in the normal manner.
In a state where "L" level is written at storage node SN of defective memory cell MC2 and "H" level is written in storage node SN of normal memory cell MC1, when word line WL2 corresponding to memory cell MC2 is pulled up to the "H" level, positive charges (holes) are introduced from word line WL2 to silicon substrate 52 through the particle. Because of this positive charges, silicon substrate 52 locally attains to positive potential, and a PN junction between the portion having the positive potential and storage node SN of memory cell MC2 is forward biased. Accordingly, negative charges (electrons) flow out from storage node SN which is at the "L" level to silicon substrate 52. The negative charges move even to the storage node SN which is at the "H" level of adjacent memory cell MC1, pulling down the storage node SN to "L" level.
Therefore, even when the defective memory cell MC is replaced by a normal memory cell MC of redundancy memory cell array 6052, DRAM may not operate properly because of possible failure of a memory cell MC near the defective memory cell MC.
It is possible to detect the defect such as described above by a test in which "L" level is written to the storage node SN of defective memory cell MC and "H" level is written to storage nodes SN of other normal memory cells MC, a word line corresponding to the defective memory cell is pulled up to "H" and data of normal memory cells MC are read thereafter. If the storage nodes SN of the normal memory cells MC are at the "H" level, it is determined that the device has passed the test, and if the storage node SN of a normal memory cell MC is inverted to the "L" level, it is determined that the device fails.
However, in the conventional DRAM, it is not possible to access the defective memory cell MC which has been replaced by the redundancy memory cell MC. Therefore, it is not possible to write "L" level to the storage node SN of the replaced defective memory cell MC.
Further, as shown in FIG. 14, since a plurality of memory cells MC of respective columns are connected to bit line BL or /BL alternately, it is necessary to switch logic levels to be applied to bit lines BL and /BL in accordance with the address of the memory cell MC even when the same logic level is to be written to the storage nodes SN of the memory cells MC. Therefore, writing of a logic level to the storage node SN of each memory cell MC has been difficult. Especially when a defective memory cell MC is replaced by a redundancy memory cell MC, there may be cases where a memory cell MC connected to bit line BL is replaced by a redundancy memory cell MC connected to bit line BL' and where it is replaced by a redundancy memory cell MC connected to bit line BL'. This makes it more difficult to write logic level to the storage node SN of the redundancy memory cell MC.
A structure of a semiconductor memory device which addresses the first problem is disclosed in U.S. Pat. No. 5,666,315.
FIG. 17 is a schematic block diagram showing a main portion of the DRAM disclosed in the aforementioned U.S. Pat. No. 5,666,315.
In FIG. 17, same reference characters as in FIG. 12 denote the same components.
Different from the prior art shown in FIG. 12, power supply lines V.sub.BL1, V.sub.BL2, . . . , V.sub.BLs for supplying precharge potential V.sub.BL for the bit lines and the line S2 of sense amplifier are arranged parallel to CS line for every unit of bit line pair group.
The precharge potential power supply lines and corresponding memory cell array portions are connected by nonvolatile switch means such as fuse elements, respectively.
Further, the line S2 is separated for each of the bit line pair group units 6100, 6102 and so on, which is a unit of replacement when there is a defective bit. An S2 line equalize circuit S2-EQ for connecting/disconnecting the pair of S2 lines is provided for each unit.
Now, when there is a short-circuit portion 6200 in a memory cell connected to bit line BL1 in bit line pair group unit 6100, for example, a fuse element 6028 is cut.
Accordingly, though there are first and second leak paths even after replacement by the unit of bit line pair group including the defective bit in the prior art example, the leak paths are cut off and leak current does not flow in accordance with the present structure.
Therefore, increase in standby current caused by the defective bit after replacement can be prevented.
FIG. 18 is a timing chart showing operation of a first embodiment.
Basically, the operation is similar to that of the conventional example shown in FIG. 13. Sensing operation is performed even for the bit line pair BL1, /BL1 connected to the defective bit, and the potential difference between the pair of bit lines is amplified.
Here, since there is leakage between bit line BL1 and the ground, bit line BL1 is amplified to the "L" level and bit line /BL1 to "H" level.
However, the bit line pair is replaced by a spare bit line pair, that is, SPARE BL1 and SPARE /BL1. Therefore, there is not a problem for the basic operation.
Thereafter, at time t.sub.9, the signal BLEQ goes from low to high and paired bit lines BL1 and /BL1 are connected to each other and attain to the level of 1/2Vcc. However, because of leakage current, the voltage level of the bit line pair gradually lowers, and at time t.sub.10, the potential is sufficiently lowered and thereafter a constant value is maintained.
Since fuse element 28 is cut, leakage current does not flow thereafter.
In the conventional redundancy circuit shown in FIG. 12, even when the bit line pair group unit including a defect is repaired, increase in standby current cannot be prevented.
By contrast, when S2 lines are isolated by the unit of replacement, the precharge power supply interconnection for the bit line and the line S2 is isolated and a leakage current path is cut by the fuse element as in the structure shown in FIG. 17, so that the first problem described above can be solved.
However, even by the DRAM having such a structure as shown in FIG. 17, the second problem cannot be solved. More specifically, since the defective memory cell MC which has been replaced by the redundancy memory cell MC cannot be accessed, a desired logic level cannot be written to the storage node SN of the replaced defective memory cell MC.